1. Field of the Invention
This invention relates to multi-layer type semiconductor devices, and more particularly to multi-layer type semiconductor devices having semiconductor element layers stacked in opposite directions. This invention relates also to methods of manufacturing such multi-layer type semiconductor devices. The invention has particular application in the field of image processing system fabricated on a single common multiple layer integrated circuit.
2. Description of the Background Art
An ordinary integrated circuit is formed on a surface of a wafer and has, so to speak, a two-dimensional structure. As distinct from this, an integrated circuit including a plurality of semiconductor layers having semiconductor elements and stacked one upon another is called a three-dimensional integrated circuit. Because of the multi-layer structure, the three-dimensional integrated circuit has the advantage of realizing a very high degree of integration and greatly improved functions.
Generally, the three-dimensional integrated circuit includes semiconductor layers and insulating layers stacked alternately, with each semiconductor layer having active elements formed therein. With the integrated circuit having active elements formed in the respective semiconductor layers formed on the insulating layers, the elements have only a small excess capacity, and hence a further advantage of enabling high speed operation of these elements.
The technique of forming semiconductor layers, particularly silicon layers, on insulating layers will be described next.
The technique of providing a structure in which silicon layers are formed on insulating layers is known as SOI (Silicon On Insulator) technique. A silicon layer formed on an insulating layer is called an SOI layer, and a structure having silicon layers formed on insulating layers an SOI structure. Such a technique is described, for example, in an article titled "Silicon-on-Insulator: Its Technology and Applications" edited by S.Furukawa and published by KTK Scientific Publishers in 1985.
As SOI techniques, methods are known which utilize epitaxy. These methods include a liquid phase epitaxy method such as a melting recrystallization method in which a polycrystalline or amorphous semiconductor layer formed on an insulating layer is exposed to and melted by energy light such as a laser beam, an electron beam or the like, and is thereafter allowed to solidify, a solid phase epitaxy method which causes an amorphous semiconductor layer to grow in solid phase, and a vapor phase epitaxy method which utilizes graphoepitaxy or bridging epitaxy. However, since these methods cause silicon crystals to grow on an insulating layer, it is difficult to obtain a single-crystal layer over a large area and to control film thickness compared with the case of causing silicon crystals to grow epitaxially on a single-crystal layer.
As a technique of obtaining the SOI structure, SIMOX (Separation by Implanted Oxygen) is known. SIMOX is a method of obtaining a structure having mutually separated semiconductor layers, in which ions such as of oxygen are injected in high concentration into a semiconductor layer to form a buried insulating layer. With this method, however, it is difficult to obtain a multi-layer structure, which makes this method hardly applicable for manufacture of a three-dimensional integrated circuit.
As another technique of obtaining the SOI structure, a wafer direct bonding method is known. Such a method is presented, for example, in "APPLICATIONS OF THE SILICON WAFER DIRECT-BONDING TECHNIQUE TO ELECTRON DEVICES" by K. Furukawa et al. in 1989 Applied Surface Science 41/42 at pp. 627-632. In the wafer direct bonding method, a wafer having an insulating layer formed on a surface thereof is superposed by a single-crystal wafer or a wafer having a single-crystal layer, and the two wafers are heat-treated (annealed) in an atmosphere of 600.degree. to 1,000.degree. C. The heat treatment induces an interatomic junction over contacting surfaces, thereby bonding the wafers together. Then the upper wafer is thinned, to complete a semiconductor layer formed on the insulating layer. The semiconductor layer obtained on the insulating layer by the wafer direct bonding method is, by origin, a product of epitaxy formed on a single-crystal silicon substrate. Thus, this semiconductor layer has an excellent crystalline property and a uniform film thickness, to be suitable for manufacture of a three-dimensional integrated circuit.
A multi-layer type semiconductor device manufactured by the above wafer direct bonding method and forming the background of this invention will be described next.
FIGS. 24A through 24K are sectional views showing a process of manufacturing the multi-layer type semiconductor device forming the background of this invention.
Referring to FIG. 24A, a first silicon wafer 101a having a thickness of 500 to 600 .mu.m includes an insulating layer 102 formed 1,000 to 10,000.ANG. thick on a surface region thereof. A second silicon wafer 101b having a thickness corresponding to that of the first silicon wafer 101a includes, formed on a surface region thereof, a boron-injected layer 103a with boron injected thereinto in a high concentration on the order of 1.times.10.sup.20 /cm.sup.3 and a low concentration epitaxial layer 104a having a thickness of about 5,000.ANG.. Boron-injected layer 103 is used as etchant stopper for a subsequent process. The epitaxial layer 104a is obtained by causing silicon crystals to grow epitaxially on the single-crystal substrate 101b.
Referring to FIG. 24B, the two wafers 101a and 101b are placed in superposition with the insulating layer 102 and epitaxial layer 104a opposed to each other, and are heat-treated in an atmosphere of about 800.degree. C. This heat treatment is called annealing. The annealing induces an interatomic junction over contacting surfaces, which bonds the two wafers 101a and 101b together. Next, an upper surface of one of the wafers 101b is coarsely polished until its thickness is reduced to 100 .mu.m. Thereafter the wafer 101b is finely etched with a mixed liquid of hydrofluoric acid and nitric acid until its thickness is reduced to 10 .mu.m.
Next, the wafer 101b is etched with an aqueous solution of ethylenediamine and pyrocatechol. The etching step using this aqueous solution is carried out at a rate of 1 .mu.m/min. for semiconductor regions having a low concentration of boron, whereas the etching progresses at a rate of 20.ANG./min. for regions of higher boron concentration. Consequently, the etching action stops at the high concentration boron- injected layer 103a. Thus, as shown in FIG. 24C, the wafer 101b is removed except the high concentration boron-injected layer 103a and epitaxial layer 104a. Next, to form semiconductor elements, the boron-injected layer 103a is etched away, and a surface thereby exposed is oxidized which is followed by a step of etching away an oxide film. This leaves a thin SOI layer 104a having a thickness on the order of 1,000.ANG..
Referring to FIG. 24D next, field oxide layers 105a are formed by LOCOS (Local Oxidation of Silicon) in regions of the SOI layer 104a which are to serve as isolation regions.
Referring to FIG. 24E next, a gate insulator film 107a is formed by oxidation of the SOI layer 104, and a polysilicon layer is formed on the gate insulator film 107a. This polysilicon layer is patterned into a shape of a gate electrode 106a. Next, impurities are applied by ion implantation using the gate electrode 106a as a mask to form source and drain regions 108a.
Referring to FIG. 24F next, an interlayer insulating film 109a is formed over the entire surface, and contact holes 110 are formed through the interlayer insulating film 109a.
Referring to FIG. 24G next, refractory metal interconnections 111 are formed as electrically connected to the source and drain regions 108a and extending onto the interlayer insulating films 109a. The gate electrode 106a, gate insulator film 107a and source and drain regions 108a constitute a transistor. Next, an insulating layer 112 is formed over the interlayer insulating film 109a and refractory metal interconnections 111.
Referring to FIG. 24H next, the insulating layer 112 is flattened for the purpose of superposition. Thereafter the flattened insulating layer 112 is superposed by a third silicon wafer 101c including a high concentration boron- injected layer 103b and an epitaxial layer 104b as does the second silicon wafer 101b. The two wafers are annealed in an atmosphere of about 800.degree. C., whereby the wafers are bonded together through surfaces of the insulating layer 112 and epitaxial layer 104b as shown in FIG. 24I.
Next, as described hereinbefore, the wafer 101c is thinned by polishing and by etching with the mixed liquid of hydrofluoric acid and nitric acid. Further, the wafer ethylenediamine and pyrocatechol. Consequently, as shown in FIG. 24J, the wafer 101c is removed except the high concentration boron-injected layer 103b and epitaxial layer 104b. The epitaxial layer 104b of the third silicon wafer 101c is used as a second SOI layer. Subsequently, to form semiconductor elements, the boron-injected layer 103a is etched away.
Referring to FIG. 24K next, field oxide layers 105b, a gate insulator film 107b, a gate electrode 106b, source and drain regions 108b, an interlayer insulating film 109b, and metal interconnections 113 comprising aluminum or an aluminum alloy are formed by using the second SOI layer 104b as a base, as described with reference to FIGS. 24D and 24E. The gate electrode 106b, gate insulator film 107b and source and drain regions 108b constitute a transistor. In this way, a first active layer L1 is formed on the semiconductor substrate 101a through the insulating layer 102, and a second active layer L2 on the first active layer L1 through the insulating layer 112. The transistor of the first active layer L1 and that of the second active layer L2 are electrically interconnected, as necessary, by conductors mounted in through holes 114.
The multi-layer type semiconductor device manufactured by the above method employs a refractory metal, instead of aluminum, for the metal interconnections of the first active layer. This is because the metal interconnections are exposed to the high temperature when the two wafers are bonded by annealing as shown in FIG. 24I. Thus, if a third active layer is formed on the second active layer, the aluminum interconnections of the second active layer L2 are replaced with the refractory metal interconnections.
In the foregoing multi-layer type semiconductor device, the active layers are stacked in a fixed direction on the basis of a surface of the semiconductor substrate. If a large number of layers are stacked, a distortion due to the fixed stacking direction becomes apparent, giving rise to the problems of fluctuating a threshold voltage and increasing leakage.
Further, since the active layers are stacked on only one surface of the substrate, the active layer close to the substrate is heated more frequently than the active layer or layers farther away from the substrate and, therefore, is required to have a better heat-resisting property.
An image processing system employing the multi-layer type semiconductor device manufactured by the foregoing method will be described next. This image processing system includes a photodetecting portion for receiving light from an object, and a display portion for displaying a received optical signal as an image.
In such an image processing system, generally, the photodetecting portion and display portion are formed separately for the following reason. It is necessary for photodetecting elements to receive light from outside, and for display elements to be visible from outside. The two types of elements must, therefore, be formed in or adjacent outwardly exposed positions. If the multi-layer semiconductor device 10 shown in FIG. 24K is applied to the image processing system, since the display elements and photodetecting elements are formed on one side of the substrate, the substrate must be transparent and the display elements are formed closest to the substrate and the photodetecting elements remotest therefrom, or, conversely, the photodetecting elements are formed closest to the substrate and the display elements remotest therefrom. Since the previously formed active layers are heated every time a new active layer is formed, the active layer close to the substrate is heated more frequently than the active layer or layers farther away from the substrate. Thus, a material having a poor heat-resisting property cannot be used for the layer close to the substrate.
If, for example, a sensor comprising an amorphous material were formed in the layer close to the substrate, this sensor would be inoperable since the amorphous material would become crystallized as a result of the long heat treatment. If a sensor comprising a pn junction were formed in the layer close to the substrate, the position of junction in the pn junction would shift or would extend deep into the semiconductor layer as a result of the long heat treatment, thereby lowering the light absorption efficiency of the sensor. Further, a liquid crystal display formed adjacent the substrate would have the liquid crystal destroyed by the heat.
In order to avoid the above setbacks, a possible consideration is that, for example, an active layer including display elements is formed on one surface of the substrate, and an active layer including sensor elements is formed on the other surface thereof. However, this construction would require through holes to be formed in the thick substrate in order to electrically interconnect the active layers formed on the opposite surfaces of the substrate. Since it is difficult to form a plurality of through holes in the substrate, this method cannot be applied to the above system which requires a high degree of integration. Thus, it is very difficult to apply the multi-layer type semiconductor device with the SOI layers stacked only on one surface of the substrate to an image processing system having a photodetecting portion and a display portion formed on a single chip. Generally, therefore, as shown in FIG. 25, a photodetecting portion 20 and a display portion 30 are fabricated separately and are electrically interconnected through leads 15.
In FIG. 25, the photodetecting portion 20 includes a substrate 201, an insulating layer 202 formed on the substrate 201 for forming an SOI layer, a three-dimensional integrated circuit 215 formed on the insulating layer 202 and having a processing circuit for processing an electric signal based on the light received by the photodetecting portion 20 and a memory circuit for storing data for comparison with the electric signal, a photoelectric sensor 216 having photodiodes arranged in matrix form, and an output circuit 217 having output pads. The three-dimensional integrated circuit 215 includes active layers L1, L2 . . . Ln forming, individually or in combination, circuits having independent functions, and signals are communicated among the layers via through holes. The display portion 30 includes a substrate 301, a switching circuit 318 having electrodes for driving a liquid crystal display, an input circuit 317 having input pads, a liquid crystal 319, a resin member 320 for sealing the liquid crystal, and a window 321.
In the image processing system shown in FIG. 25, the photoelectric sensor 216 of the photodetecting portion 20 receives light traveling in the direction of arrow A from an object, and converts it into an electric signal. This electric signal is electrically processed by the three-dimensional integrated circuit 215 for contour extraction and highlighting, pattern recognition and the like. This electric signal is transferred from the output pads 217 of the output circuit such as a shift register through the leads 15 to the input pads 317 of the display portion 30. In the display portion 30, the liquid crystal 319 is driven in response to the signal transferred, to display a figure such as of contour lines. The displayed figure is visible through the window 321 in the direction of arrow B.
A method of manufacturing the photodetecting portion and display portion of the image processing system shown in FIG. 25 will be described in outline next.
Referring to FIG. 26A, the photodetecting portion is manufactured by forming the three-dimensional integrated circuit 215, which carries out image processing, on the insulating layer 202 superposed on the silicon substrate 201 in the same way as described with reference to FIGS. 24A through 24K. Referring next to FIG. 26B, the photoelectric sensor 216 and the output circuit 217 having the output pads are formed on the three-dimensional integrated circuit 215.
Referring to FIGS. 26C and 26D, the display portion is manufactured by forming, on the substrate 301, the switching circuit 318 having the electrodes for driving the liquid crystal display, and the input circuit 317 having the input pads. Then the resin member 320 for sealing the liquid crystal is mounted in position, and the transparent window 321 is attached to the resin member 320. Subsequently, pressure in a gap between the switching circuit 318 and window 321 is reduced to introduce the liquid crystal 319 therein.
A sensing system employing the foregoing multi-layer type semiconductor device having the three-dimensional integrated circuit will be described next. This sensing system includes a sensor provided at an input side for detecting light, pressure, temperature or radiation, and light emitting elements such as light emitting diodes at an output side for displaying sensing results. Such a sensing system is shown in FIG. 27.
In FIG. 27, a sensor portion 40 includes a substrate 401, an insulating layer 402 formed on the substrate 401 for forming an SOI layer, a three-dimensional integrated circuit 415 formed of a plurality of active layers L1, L2 . . . Ln and having a processing circuit for processing information detected by the sensor portion 40, and an output circuit 417 having output pads. An output portion 50 includes a substrate 501, display elements 522 which are red, green and blue light emitting diodes arranged in matrix form, and an input circuit 517 having input pads.
This sensing system is manufactured by the following method. As shown in FIG. 28A, the insulating layer 402 is formed on the substrate 401, and the three-dimensional integrated circuit 415 is formed on the insulating layer 402. Then, as shown in FIG. 28B, the sensor 416 and the output circuit 417 having the output pads are formed.
As shown in FIGS. 28C and 28D, the display elements 522 which are the light emitting diodes arranged in matrix form, and the input circuit 517 having the input pads are formed on the substrate 501. Next, the output pads 417 and input pads 517 are interconnected by leads 15. This completes the sensing system having a sensing function and a displaying function.
The foregoing image processing system or sensing system may be classified broadly into two types by a difference in displaying mode.
The first type, as shown in FIG. 29, has a photodetecting portion 20 and a display portion 30 formed of materials penetrable to light, and a transmitted image of an object 25 to be detected and an image based on results of processing are superimposed when seen by the naked eye 35. The transmitted image herein refers to an image of the object 25 visible through the photodetecting portion 20 and display portion 30, and the image based on results of processing refers to an image displayed on a liquid crystal 319. With this type of system, a precise positional adjustment between the photodetecting portion 20 and display portion 30 is necessary for the transmitted image and the image based on results of processing to be seen in perfect register.
In the second type, as shown in FIGS. 30 and 31, only the image displayed on the display portion 30 or 50 can be seen by the naked eye 35. This type of system provides no transmitted image of the object 25.
FIG. 30 shows a system employing the liquid crystal 319 as the display device, while FIG. 31 shows a system employing the light emitting element 522. Particularly where the signal processing function of the three-dimensional integrated circuit 215 or 415 is jeopardized by external light or light from the object 25, a light shielding film 224 or 424 is inserted between the sensor 216 or 416 and three-dimensional integrated circuit 215 or 415.
The second type of system using a liquid crystal as the display device may be further classified into the reflection type and the transmission type. As shown in FIG. 30, the reflection type includes a reflecting film provided on a rear surface of the liquid crystal 319 to give a display by light reflected from the reflecting film on the rear surface of the liquid crystal 319. As shown in FIG. 32, the transmission type includes a light source 323 disposed behind the liquid crystal 319 to give a display by transmitted light passing through the liquid crystal 319. The reflection type shown in FIG. 30 employs a material having high reflectance, such as a silicon substrate, as the substrate 301a of the display portion 30.
The transmission type shown in FIG. 32 employs a transparent substrate as the substrate 301b of the display portion 30, and includes a light emitter 323 outwardly of the transparent substrate 301b. However, in this case too, the light from the light emitter 323 will enter the three-dimensional integrated circuit 215 to jeopardize its signal processing function if a substrate 201b and an insulating layer 202b are penetrable to light. In order to avoid such trouble, it is necessary to provide a light shielding plate 324 between the light emitter 323 and photodetecting portion 20 as shown in FIG. 33, or to employ a light shielding material as the substrate 201c of the photodetecting portion 20.
Where the signal processing function of the three-dimensional integrated circuit 215 is jeopardized by external light or light from the object 25, a light shielding film 224 or 424 must be inserted between the sensor layer 216 and three-dimensional integrated circuit 215 as in the systems shown in FIGS. 30 and 31.
Further, where the foregoing liquid crystal display device is employed, there is a disadvantage of enlarging the system configuration since it is necessary to incorporate a light emitter.
The image processing system or sensing system employing the multi-layer type semiconductor device with active layers stacked only on one surface of a semiconductor substrate, as described above, has the sensor portion and display portion fabricated on separate chips, which results in the following disadvantage. There are a serial transmission system and a parallel transmission system for transferring signals between the two chips. A transfer of the signals in serial transmission is time-consuming and makes real-time processing impossible. A parallel transfer of the signals necessitates numerous input and output pads to be provided on each chip, which inevitably leads to an increased chip area.
The manner in which the input and output pads of the multi-layer type semiconductor device forming the background of this invention are arranged will be described next.
FIG. 34A is a plan view of the multi-layer type semiconductor device, FIG. 34B is a bottom view thereof, and FIG. 34C is a section taken on line C--C of FIG. 34A. As shown in FIG. 34A through 34C, pads 617a and 617b are provided only on one side of the multi-layer type semiconductor device 60, with no pads provided on the other side.
As shown in FIG. 34C, a first active layer 615a is formed on a substrate 601a, and a second active layer 615b is formed on the first active layer 615a through an insulating layer 612. The first active layer 615a and second active layer 615b include electric circuits serving the purpose for which the semiconductor device 60 is intended. The electric circuit in the first active layer 615a and the electric circuit in the second active layer 615b are electrically interconnected by conductors mounted in through holes 614b. Refractory metal interconnections 611 are led out of the electric circuit formed in the first active layer 615a. Pads 617a are formed on the insulating layer 612, and aluminum interconnections 613a extend from the pads 617a. These interconnections 613a are electrically connected to the refractory metal interconnections 611 by conductors mounted in through holes 614a. Aluminum interconnections 613b are led out of the electric circuit formed int he second active layer 615b. These aluminum interconnections 613b are electrically connected to pads 617b formed on the insulating layer 612.
Of the pads arranged around the electric circuit 615b shown in FIG. 34A, the outer pads 617a correspond to the first active layer 615a and the inner pads 617b to the second active layer 615b. Pads 617a are used, for example, as input pads while pads 617a are used, for example, as output pads. In this case, signals input through the pads 617b are processed by the two-layer electric circuit 615b and 615a and output through pads 617a.
FIGS. 35A through 35E are sectional views illustrating a method of manufacturing the multi-layer type semiconductor device 60 shown in FIGS. 34A and 34C. The method of manufacturing the multi-layer type semiconductor device will be described next with reference to FIGS. 35A through 35E.
Referring to FIGS. 35A and 35B, the first active layer 615a is formed on the substrate 601a by the method shown in FIGS. 24A through 24G. The substrate comprises a semiconductor substrate or quartz. Next, an electric circuit comprising semiconductor elements is formed in the active layer 615a, and the refractory metal interconnections 611 are formed as electrically connected to the electric circuit.
Referring to FIG. 35C next, the insulating layer 612 is formed over an entire surface of the substrate 601a, which is then flattened.
Referring to FIG. 35D next, a substrate 601b having an epitaxial layer 604 formed on one side thereof is superposed on the insulating layer 612, and the substrates 601a and 601b are bonded together by annealing in an atmosphere of about 800.degree. C. Thereafter, the substrate 601b is thinned down to expose the epitaxial layer 604 by the same method as described with reference to FIG. 24I.
Referring to FIG. 35E next, the second active layer 615b is formed on the epitaxial layer 604 acting as the base, an electric circuit comprising semiconductor elements is formed on the active layer 604 acting as the base, an electric circuit comprising semiconductor elements is formed on the active layer 615b, and the electric circuits of the first and second active layers are interconnected via through holes 614b formed in the insulating layer 612. On the insulating layer 612 are formed the aluminum interconnections 613b electrically connected to the electric circuit of the second active layer, and the pads 617b electrically connected to the aluminum interconnections 613b. Further, on the insulating layer 612 are formed the pads 617a, and aluminum interconnections 613a electrically connected to the pads 617a and electrically connected via the through holes 614a to the interconnections 611.
As described above, the multi-layer type semiconductor device forming the background of this invention has the pads formed only on one surface of a chip. Thus, there is a problem of having to enlarge the chip area when providing a large number of pads.
The multi-layer type semiconductor device forming the background of this invention, because the SOI layers or active layers are stacked in a fixed direction, has various disadvantages as follows:
(1) Where a large number of layers are stacked, a distortion due to the stacking in a fixed direction, that is, stacking from only one side of the substrate becomes apparent, which results in fluctuations of a threshold voltage and an increase in leakage.
(2) A possible consideration is that, where necessary, SOI layers stacked in a fixed direction are formed on one surface of a substrate, and an active layer or layers are formed on the other surface thereof, the latter being electrically connected to the elements formed in the SOI layers. However, it is difficult to form a plurality of through holes in the thick substrate.
(3) In a system comprising a photodetecting portion or sensor portion and a display portion, the stacked SOI layers must include a sensor layer and a display layer located closest to and remotest from the substrate. It is, therefore, difficult to realize an image processing system or a sensing system formed on a single chip.
(4) That the sensor portion and display portion must be formed on separate chips entails the following disadvantages. It is difficult to transfer a large amount of data at high speed. A positional adjustment must be effected in order to place an object detected and an image displayed in register. Furthermore, the device per se has a large configuration.
(5) Since the input and output pads are formed only on one surface of the substrate, an increase in the number of input and output pads results in a large chip configuration.